PIC16F87T-E/SS【PDF 187/200 页】IC MCU FLASH 4KX14 EEPROM 20SSOP

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Sheet目录3882

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8008H–AVR–04/11

ATtiny48/88

11.8.4

OCR0B – Output Compare Register B

The Output Compare Register B contains an 8-bit value that is continuously compared with the

counter value (TCNT0). A match can be used to generate an Output Compare interrupt.

11.8.5

TIMSK0 – Timer/Counter Interrupt Mask Register

Bits 7:3 – Res: Reserved Bits

These bits are reserved and will always read zero.

Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable

When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if

a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter

Interrupt Flag Register – TIFR0.

Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable

When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed

if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the

Timer/Counter 0 Interrupt Flag Register – TIFR0.

Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an

overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Inter-

rupt Flag Register – TIFR0.

11.8.6

TIFR0 – Timer/Counter 0 Interrupt Flag Register

Bits 7:3 – Res: Reserved Bits

These bits are reserved and will always read zero.

Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag

The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in

OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the cor-

responding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to

the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable),

and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.

Bit

654

0x28 (0x48)

OCR0B[7:0]

OCR0B

Read/Write

R/W

Initial Value

Bit

(0x6E)

–

OCIE0B

OCIE0A

TOIE0

TIMSK0

Read/Write

RRRR

R/W

Initial Value

Bit

654

0x15 (0x35)

–

OCF0B

OCF0A

TOV0

TIFR0

Read/Write

R/W

Initial Value

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